Phase locked loop (PLL) circuits are used in a variety of applications. FIG. 1 is a diagram of a conventional analog PLL circuit 100. The VCO frequency fVCO is divided by a frequency divider 112 to get the divided VCO frequency fVCO/N. A flip-flop based phase frequency detector 104 compares a reference clock “fref”, obtains the divided VCO frequency “fVCO/N” and sends charge-up and charge-down signals to adjust the analog charge-pump 106. The charge-pump 106 adjusts the control voltage up or down based on the phase frequency detector 104 comparison results. The charge-pump 106 output voltage is low pass filtered by analog filter 108 and sent to the VCO 110 so as to tune the VCO frequency.
Conventional Analog PLL Circuit function
In the conventional analog PLL circuit 100 shown in FIG. 1, the flip-flop based phase frequency detector 104 compares the frequencies of reference clock “fref” and the divided VCO frequency “fVCO/N” to adjust the charge-pump circuit 106 so as to tune the VCO frequency.
FIG. 2 illustrates a slower VCO adjusted by the conventional analog PLL circuit 100. If the VCO frequency is slower than expected, the divided VCO frequency fVCO/N arrive later than the reference clock “fref”. The phase frequency detector 104 sends a longer charge-up time signal and another shorter charge-down time signal to the analog charge-pump 106. Consequently, a positive net charge is delivered to the analog filter 108 from the charge-pump 106, which means the VCO 110 input control voltage goes up. Finally, a higher control voltage speeds up the VCO 110.
However, as device sizes become smaller such as in deep submicron technology, there are problems with this conventional analog design. Namely: (1) a relative large loop analog filter and (2) a low power supply headroom. The ways for overcoming these issues usually cause additional problems, which are described below.
1. Large loop filter size in analog PLL circuit solutions.
a) Provide a large built-in passive loop filter. The problem with this type of filter is that the filter dominates the silicon size and becomes problematic when utilized in the deep sub-micron process technology due to size conventions of the
PLL circuit 100.
b) Provide a built-in active loop filter. The problem with this type of filter is that the filter consumes a large amount of power and also creates a large amount of noise.
c) Provide a large passive loop filter outside the chip. The problem with this type of filter is that the filter provides a low integration level and also adds a package interface noise interference component.
2. Low power supply headroom.
a) When using the above-identified topology in smaller process technologies, the tunable range, noise, and linearity performances are sacrificed due to the low voltage supply headroom of the analog charge-pump.
b) Another solution is to use auxiliary circuits to correct for the tuning range, noise, and linearity issues of the charge-pump. The problem with using auxiliary circuits is that the circuits increase the size, power, and complexity of the design; and also the auxiliary circuits may become the source of additional noise and non-linearity.
To address the above-identified issues, digital PLL circuits have been implemented. FIG. 3 illustrates one embodiment of a conventional digital PLL circuit 200 that attempts to address some of the above-identified issues related to analog PLL circuits.
The conventional digital PLL circuit 200 of FIG. 3 utilizes a Time-to-Digital converter (TDC) 205 to replace the analog charge-pump so that the other blocks can be implemented in digital. The digital PLL circuit 200 does not require a frequency divider. The DCO high frequency output is sent directly to the TDC to form a feedback loop.
There are several problems with the digital PLL circuit 100 which are described below.
1. The coarse resolution (one delay time of the inverter) of the TDC limits the phase noise and jitter performances.
2. The TDC limited length limits the PLL locking range.
3. The over-sampling design consumes huge power and limits the operating frequency of the DCO 210 (PLL output frequency).
Accordingly, what is needed is a system and method for addressing the above-identified issues.
The system and method should avoid using analog circuits that dominate the silicon size. In the new deep sub-micron process technologies, the sizes of analog circuits do not shrink as digital counterparts do. The non-shrunk analog circuit size implemented with expensive new technology will increase the cost of the chips. For example, the analog charge-pump and loop filter dominate the size of conventional PLL circuit.
The low power supply voltage of the deep sub-micron process technology suppresses the headroom of circuits. The low headroom issue degrades the performance of analog circuits. The interface between phase frequency detector and high voltage analog charge-pump in an analog PLL circuit has a voltage level shift issue as well, which degrades the linearity and noise performance. Accordingly, interfaces between analog devices and digital devices that degrade the performance should be minimized.
Accordingly, a system and method is needed to address the above-identified issues. The present invention addresses such a need.